1. Field of the Invention
The present invention relates to a data input-output circuit and a semiconductor data storage device provided with the data input-output circuit in which it is possible to improve the speed of the data input-output operation in the semiconductor data storage device connected to a bus.
2. Description of the related art
The semiconductor memories such as DRAMs (Dynamic Random Access Memory), SRAMs (Static Random Access Memory) are provided with input-output terminals as indispensable terminals. Necessary data is input or output through the input-output terminals. There are several types of semiconductor memories from the view point of the configuration of the input-output terminals. Namely, (1) the input terminals and the output terminals are separately provided in the case of one type while (2) common terminals serve as the input terminals when data is to be written into the memory and serves as the output terminals when data is to be read from the memory in the case of another type. In the case of the type (2), the input-output common terminals are connected to both the output nodes of the output buffers and the input nodes of the input buffers. The input-output common terminals serve as the input terminals when data is to be written (input) into the memory and serve as the output terminals when data is to be read (output) from the memory. Accordingly, when data is to be written into the memory, the output of the output buffer has to be changed to a high impedance state so that the output buffer and the input-output common terminals have to be electrically disconnected. On the other hand, the memory of the type (1) with separate input and output terminals, a single bus is sometimes shared by a plurality of memories. In this case, when the output signal of the respective memory has to be selectively transferred to the bus, the output buffers of other memories have to be separated from the output terminals by changing the outputs of the output buffers to the high impedance state.
The output of the output buffer is changed to the high impedance state in an appropriate time during operation of the data input-output circuit of the semiconductor memory so that the output buffer is electrically separated from the input-output terminal in this manner. This control operation is called the Hi-Z control (high impedance state control) in the followings.
Next, with reference to FIG. 1, the Hi-Z control will be explained. FIG. 1 is a block diagram showing an example of the prior art data input-output circuits for use in semiconductor memories. An input-output terminal 101 is connected to both an output node of an output buffer 102 and an input node of an input buffer 103 in the data input-output circuit as illustrated in FIG. 1. Namely, the input-output terminal 101 is an input-output common terminal. The input nodes of the output buffer 102 are connected to a Hi-Z control circuit 104. The Hi-Z control circuit 104 serves to conduct the Hi-Z control for the output buffer 102. The output buffer 102 as illustrated in FIG. 1 consists of n-type MOS transistors 105 and 106 while the Hi-Z control circuit 104 consists of 2-input NOR gate circuit 107 and 108 and an inverter circuit 109.
In the case of the data input-output circuit as illustrated in FIG. 1, the output of the output buffer 102 is changed to the Hi-Z state when an output enable signal (/OE) is in the "H" level. Namely, when the output enable signal /OE is changed to the "H" level signal, the "L" level signal is output from the 2-input NOR gate circuit 107 and 108 each of which receives the output enable signal /OE at one input node thereof, irrespective of the input level at the other input node. Accordingly, the n-type MOS transistors 105 and 106 become non-conductive by receiving the output signals of the 2-input NOR gate circuits 107 and 108. The output of the output buffer 102 is then changed to the Hi-Z state.
On the other hand, when the output enable signal /OE is changed to the "L" level, the data input-output circuit outputs data latched by a register 110 to the input-output terminal 101 through the output buffer 102. For example, in the case that the "H" level data is latched by the register 110, the "L" level signal and the "H" level signal are input respectively to the input nodes of the NOR gate circuit 107 while the "L" level signals are input to both the input nodes of the NOR gate circuit 108. At this time, the NOR gate circuit 107 outputs the "L" level signal while the NOR gate circuit 108 outputs the "H" level signal. Accordingly, the "L" level signal of the NOR gate circuit 107 is input to the gate of the n-type MOS transistor 105, which is then changed to the non-conductive state. On the other hand, the "H" level signal of the NOR gate circuit 108 is input to the gate of the MOS transistor 106, which is then changed to the conductive state. The input-output terminal 101 is connected to the ground level through the n-type MOS transistor 106 and receives the "L" level signal.
However, there are shortcomings in the prior art data input-output circuit in as follows. The output enable signal /OE is generated by an output enable signal control circuit 111 in synchronism with the clock signal CLK. On the other hand, the register 110 receives the clock signal CLK and outputs data in synchronism with the clock signal CLK. Accordingly, the Hi-Z control as conducted by the Hi-Z control circuit 104 and the outputting operation of the register 110 are synchronized with each other. However, it is sometimes the case that the output enable signal control circuit 111 outputs the output enable signal /OE with a skew resulting in timing mismatch between the clock signal CLK and the output enable signal /OE as generated. Because of this, in the actual case, the Hi-Z control as conducted by the Hi-Z control circuit 104 and the outputting operation of the register 110 are not exactly synchronized with each other.
FIG. 2 is a timing chart showing data outputting operation of the data input-output circuit as illustrated in FIG. 1. There is a time interval between the time at which the output of the output buffer 102 becomes the Hi-Z state and the time at which the output buffer 102 stops outputting data "D3", as illustrated in FIG. 2. Ideally speaking, the data outputting period as defined by the output enable signal /OE shall terminate in the time at which the output buffer 102 stops outputting data "D3". However, in the actual case, the data outputting period is elongated by time t1. This mismatch results in the undesirable operation that the use of the input-output terminal 101 is released only with delay time t1. The next operation (e.g., data input operation) is therefore postponed by the delay time t1. Furthermore, for the same reason, the time delay between the rising edge of the clock signal CLK and the start of outputting data "D1" is longer than the time delay between the rising edge of the clock signal CLK and the start of outputting data "D2" and the time delay between the rising edge of the clock signal CLK and the start of outputting data "D3" for only time t2. This is one of major problems in the quest for faster data transfer between a memory and a processor in a computer system.